`timescale 1ns / 1ps
module axil_interface_test;

    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 16;

    logic clk;
    logic rst;

    logic write_en;
    logic read_en;
    logic req_valid;
    logic resp_valid;
    logic busy;
    logic ready;

    
    logic[ADDR_WIDTH-1:0] req_addr;
    logic[DATA_WIDTH-1:0] req_data;
    logic[ADDR_WIDTH-1:0] resp_addr;
    logic[DATA_WIDTH-1:0] resp_data;

    // todo
    //assign resp_addr = req_addr;
    //assign resp_data = req_data;

    axil_interface axi_inter0(
        .clk(clk),
        .rst(rst),
        .write_en(write_en),
        .read_en(read_en),
        .req_valid(req_valid),
        .ready(ready),
        .busy(busy),
        .resp_valid(resp_valid),
        .req_addr(req_addr[15:0]),
        .req_data(req_data),

        .resp_addr(resp_addr[15:0]),
        .resp_data(resp_data)
    );


    initial begin
        $display("test reset\n");
        clk = 0;
        rst = 1;
        write_en = 0;
        read_en = 0;
        req_valid = 0;
        ready = 0;
        # 10
        $display("test reset over\n");
        rst = 0;
        # 10
        write_en = 1;
        req_valid = 1;
        ready = 0;
        req_addr = 16'h0010;
        req_data = 32'hDEAD_BEEF;
        # 10
        # 10
        # 10
        # 10
        # 10
        ready = 1;
        write_en = 0;
        req_valid = 0;
        req_data = 0;
        # 10
        read_en = 1;
        req_valid = 1;
        ready = 0;
        req_addr = 16'h0010;
        # 10
        # 10
        # 10
        # 10
        # 10
        ready = 1;
        read_en = 0;
        req_valid = 0;
        # 20
        $stop
        ;
    end

    always begin
        #5 clk = ~clk;
    end


endmodule
